? die datasheet GA10JT06-CAL august 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg1 of 5 s d g normally ? off silicon carbide junction transistor features ? 250c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature co-efficient of r ds,on ? suitable for connecting an anti-parallel diode ? advantages applications ? compatible with si mosfet/igbt gate-drivers ? > 20 s short-withstand capability ? lowest-in-class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? ? hybrid electric vehicles (hev) ? solar inverters ? switched-mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives absolute maximum ratings parameter symbol conditions value unit notes drain ? source voltage v ds v gs = 0 v 600 v continuous drain current i d t c = 25c 25 a continuous gate current i gm 3 a turn-off safe operating area rbsoa t vj = 250 o c, i g = 1 a, clamped inductive load i d,max = 10 @ v ds v dsmax a short circuit safe operating area scsoa t vj = 225 o c, i g = 2.5 a, v ds = 400 v, non repetitive > 20 s reverse gate ? source voltage v sg 30 v reverse drain ? source voltage v sd 25 v storage temperature t stg -55 to 250 c electrical characteristics on state characteristics ? off state characteristics ? ?? v ds = 600 v r ds(on) = 120 m i d (tc = 25c) = 25 a h fe(tc = 25c) = 120 parameter symbol conditions value unit notes min. typical max. drain ? source on resistance r ds(on) i d = 10 a, t j = 25 c i d = 10 a, t j = 125 c i d = 10 a, t j = 175 c i d = 10 a, t j = 225 c 120 180 240 320 m ? fig. 5 gate forward voltage v gs(fwd) i g = 500 ma, t j = 25 c i g = 500 ma, t j = 225 c 2.95 2.63 v fig. 4 dc current gain v ds = 5 v, i d = 10 a, t j = 25 c v ds = 5 v, i d = 10 a, t j = 125 c v ds = 5 v, i d = 10 a, t j = 175 c v ds = 10 v, i d = 10 a, t j = 225 c 123 87 80 76 ? fig. 5 drain leakage current i dss v r = 600 v, v gs = 0 v, t j = 25 c v r = 600 v, v gs = 0 v, t j = 125 c v r = 600 v, v gs = 0 v, t j = 225 c 10 50 100 a fig. 6 gate leakage current i sg v sg = 20 v, t j = 25 c 20 na
? die datasheet GA10JT06-CAL august 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg2 of 5 figures figure 1: typical output characteristics at 25 c figure 2: typical output characteristics at 125 c figure 3: typical output characteristics at 225 c figure 4: typical gate source i-v characteristics vs. temperature figure 5: normalized on-resistance and current gain vs. temperature figure 6: typical blocking characteristics
? die datasheet GA10JT06-CAL august 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg3 of 5 gate drive theory of operation the sjt transistor is a current controlled transistor which requires a positive gate curr ent for turn-on as well as to remain i n on-state. an ideal gate current waveform for ultra-fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 9. figure 9: idealized gate current waveform gate currents, i g,pk /-i g,pk and voltages during turn-on and turn-off an sjt is rapidly switched from its blocking state to on-state, when the necessary gate charge, q g , for turn-on is supplied by a burst of high gate current, i g,on , until the gate-source capacitance, c gs , and gate-drain capacitance, c gd , are fully charged. , the i g,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the package and drive circuit. a voltage developed across the parasitic i nductance in the source path, l s , can de-bias the gate-source junc tion, when high drain currents begin to flow through the device. the applied gate voltage should be maintained high enough, above the v gs,on level to counter these effects. a high negative peak current, -i g,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. while sati sfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn-off transition. steady on-state after the device is turned on, i g may be advantageously lowered to i g,steady for reducing unnecessary gate drive losses. the i g,steady is determined by noting the dc current gain, h fe , of the device the desired i g,steady is determined by the peak device junction temperature t j during operation, drain current i d , dc current gain h fe , and a 50 % safety margin to ensure operating the device in the satu ration region with low on-state voltage drop by the equation: , , 1.5
? die datasheet GA10JT06-CAL august 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg4 of 5 mechanical specifications mechanical parameters raster size 2.10 x 2.10 mm 2 83 x 83 mil 2 a rea total / active 4.41/3.31 mm 2 6836/5134 mil 2 thickness 360 m 14 mil wafer size 100 mm 3937 mil flat position 0 deg 0 deg passivation frontside polyimide pad metal (anode) 4000 nm al backside metal (cathode) 400 nm ni + 200 nm au -system die bond electrically conductive glue or solder wire bond al 10 mil (source) al 3 mil (gate) reject ink dot size 0.3 mm recommended storage environment store in original container, in dry nitrogen, < 6 months at an ambient temperature of 23 c chip dimensions: mm mil die a 2.10 83 b 2.10 83 source wirebondable c 1.47 58 d 1.52 60 e 0.17 7 f 0.40 16 gate wirebondable g 0.30 12 h 0.30 12
? die datasheet GA10JT06-CAL august 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg5 of 5 revision history date revision comments supersedes 2014/08/26 1 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specificat ions and data in this document without noti ce. genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or i mplied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic cont rol and weapons systems, nor in applications where their failure may result in death , personal injury and/or property damage.
? die datasheet GA10JT06-CAL aug 2014 http://www.genesicsemi.com/high-temperat ure-sic/high-temperature-sic-bare-die/ pg 1 of 1 spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website ( http://www.genesicsemi.com/images/hit_ sic/baredie/sjt/GA10JT06-CAL_spice.pdf ) into ltspice (version 4) software for simulation of the GA10JT06-CAL. * model of genesic semiconductor inc. * * $revision: 2.0 $ * $date: 26-aug-2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2014 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga10jt06 npn + is 4.4e-48 + ise 1.858e-28 + eg 3.23 + bf 125 + br 0.55 + ikf 400 + nf 1 + ne 2 + rb 7.0 + re 0.005 + rc 0.105 + cjc 3.96e-10 + vjc 3.189 + mjc 0.469 + cje 8.083e-10 + vje 3.1441 + mje 0.4308 + xti 3 + xtb -0.9 + trc1 1.0e-2 + vceo 600 + icrating 10 + mfg genesic_semiconductor * * end of ga10jt06 spice model
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